84 lines
1.9 KiB
OpenEdge ABL
84 lines
1.9 KiB
OpenEdge ABL
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IFND ADDITIONALINCLUDES_HARDWARE_BLITBITS_I
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ADDITIONALINCLUDES_HARDWARE_BLITBITS_I SET 1
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BLTCON0B_ASH3 = 15
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BLTCON0B_ASH2 = 14
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BLTCON0B_ASH1 = 13
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BLTCON0B_ASH0 = 12
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BLTCON0B_USEA = 11
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BLTCON0B_USEB = 10
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BLTCON0B_USEC = 9
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BLTCON0B_USED = 8
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BLTCON0B_LF7 = 7
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BLTCON0B_LF6 = 6
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BLTCON0B_LF5 = 5
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BLTCON0B_LF4 = 4
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BLTCON0B_LF3 = 3
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BLTCON0B_LF2 = 2
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BLTCON0B_LF1 = 1
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BLTCON0B_LF0 = 0
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BLTCON0F_ASH3 = 1<<BLTCON0B_ASH3
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BLTCON0F_ASH2 = 1<<BLTCON0B_ASH2
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BLTCON0F_ASH1 = 1<<BLTCON0B_ASH1
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BLTCON0F_ASH0 = 1<<BLTCON0B_ASH0
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BLTCON0F_USEA = 1<<BLTCON0B_USEA
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BLTCON0F_USEB = 1<<BLTCON0B_USEB
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BLTCON0F_USEC = 1<<BLTCON0B_USEC
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BLTCON0F_USED = 1<<BLTCON0B_USED
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BLTCON0F_LF7 = 1<<BLTCON0B_LF7
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BLTCON0F_LF6 = 1<<BLTCON0B_LF6
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BLTCON0F_LF5 = 1<<BLTCON0B_LF5
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BLTCON0F_LF4 = 1<<BLTCON0B_LF4
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BLTCON0F_LF3 = 1<<BLTCON0B_LF3
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BLTCON0F_LF2 = 1<<BLTCON0B_LF2
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BLTCON0F_LF1 = 1<<BLTCON0B_LF1
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BLTCON0F_LF0 = 1<<BLTCON0B_LF0
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BLTCON1B_BSH3 = 15
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BLTCON1B_BSH2 = 14
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BLTCON1B_BSH1 = 13
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BLTCON1B_BSH0 = 12
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; in Area mode
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BLTCON1B_DOFF = 7
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BLTCON1B_EFE = 4
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BLTCON1B_IFE = 3
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BLTCON1B_FCI = 2
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BLTCON1B_DESC = 1
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BLTCON1B_LINE = 0
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; in Fill mode
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BLTCON1B_DPFF = 7
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BLTCON1B_SIGN = 6
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BLTCON1B_OVF = 5
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BLTCON1B_SUD = 4
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BLTCON1B_SUL = 3
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BLTCON1B_AUL = 2
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BLTCON1B_SING = 1
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;BLTCON1B_LINE = 0
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BLTCON1F_BSH3 = 1<<BLTCON1B_BSH3
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BLTCON1F_BSH2 = 1<<BLTCON1B_BSH2
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BLTCON1F_BSH1 = 1<<BLTCON1B_BSH1
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BLTCON1F_BSH0 = 1<<BLTCON1B_BSH0
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; in Area mode
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BLTCON1F_DOFF = 1<<BLTCON1B_DOFF
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BLTCON1F_EFE = 1<<BLTCON1B_EFE
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BLTCON1F_IFE = 1<<BLTCON1B_IFE
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BLTCON1F_FCI = 1<<BLTCON1B_FCI
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BLTCON1F_DESC = 1<<BLTCON1B_DESC
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BLTCON1F_LINE = 1<<BLTCON1B_LINE
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; in Fill mode
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BLTCON1F_DPFF = 1<<BLTCON1B_DPFF
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BLTCON1F_SIGN = 1<<BLTCON1B_SIGN
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BLTCON1F_OVF = 1<<BLTCON1B_OVF
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BLTCON1F_SUD = 1<<BLTCON1B_SUD
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BLTCON1F_SUL = 1<<BLTCON1B_SUL
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BLTCON1F_AUL = 1<<BLTCON1B_AUL
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BLTCON1F_SING = 1<<BLTCON1B_SING
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;BLTCON1F_LINE = 1<<BLTCON1B_LINE
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ENDC ; ADDITIONALINCLUDES_HARDWARE_BLITBITS_I
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