Fixed addressing modes. Added missing generated class, removed unused one.
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@@ -20,14 +20,14 @@ object M68kIsa {
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val isaData = listOf(
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IsaData("abcd", "Add Decimal with Extend"),
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IsaData("add", "Add"),
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IsaData("adda", "Add Address"),
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IsaData("addi", "Add Immediate"),
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IsaData("adda", "Add Address", altMnemonics = listOf("add")),
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IsaData("addi", "Add Immediate", altMnemonics = listOf("add")),
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IsaData("addq", "Add Quick"),
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IsaData("addx", "Add with Extend"),
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IsaData("and", "Logical AND"),
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IsaData("andi", "Logical AND Immediate"),
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IsaData("andi", "to CCR AND Immediate to Condition Code Register"),
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IsaData("andi", "to SR AND Immediate to Status Register"),
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IsaData("andi", "Logical AND Immediate", altMnemonics = listOf("and")),
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IsaData("andi", "to CCR AND Immediate to Condition Code Register", altMnemonics = listOf("and")),
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IsaData("andi", "to SR AND Immediate to Status Register", altMnemonics = listOf("and")),
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IsaData("asl", "Arithmetic Shift Left"),
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IsaData("asr", "Arithmetic Shift Right"),
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IsaData("bCC", "Branch Conditionally", conditionCodes = conditionCodesBcc),
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@@ -40,9 +40,9 @@ object M68kIsa {
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IsaData("chk", "Check Register Against Bound"),
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IsaData("clr", "Clear"),
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IsaData("cmp", "Compare"),
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IsaData("cmpa", "Compare Address"),
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IsaData("cmpi", "Compare Immediate"),
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IsaData("cmpm", "Compare Memory to Memory"),
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IsaData("cmpa", "Compare Address", altMnemonics = listOf("cmp")),
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IsaData("cmpi", "Compare Immediate", altMnemonics = listOf("cmp")),
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IsaData("cmpm", "Compare Memory to Memory", altMnemonics = listOf("cmp")),
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IsaData(
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"dbCC",
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"Test Condition, Decrement, and Branch",
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@@ -52,9 +52,9 @@ object M68kIsa {
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IsaData("divs", "Signed Divide"),
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IsaData("divu", "Unsigned Divide"),
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IsaData("eor", "Logical Exclusive-OR"),
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IsaData("eori", "Logical Exclusive-OR Immediate"),
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IsaData("eori", "to CCR Exclusive-OR Immediate to Condition Code Register"),
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IsaData("eori", "to SR Exclusive-OR Immediate to Status Register"),
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IsaData("eori", "Logical Exclusive-OR Immediate", altMnemonics = listOf("eor")),
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IsaData("eori", "to CCR Exclusive-OR Immediate to Condition Code Register", altMnemonics = listOf("eor")),
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IsaData("eori", "to SR Exclusive-OR Immediate to Status Register", altMnemonics = listOf("eor")),
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IsaData("exg", "Exchange Registers"),
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IsaData("ext", "Sign Extend"),
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IsaData("illegal", "Take Illegal Instruction Trap"),
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@@ -65,7 +65,7 @@ object M68kIsa {
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IsaData("lsl", "Logical Shift Left"),
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IsaData("lsr", "Logical Shift Right"),
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IsaData("move", "Move"),
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IsaData("movea", "Move Address"),
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IsaData("movea", "Move Address", altMnemonics = listOf("move")),
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IsaData("move", "to CCR Move to Condition Code Register"),
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IsaData("move", "from SR Move from Status Register"),
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IsaData("move", "to SR Move to Status Register"),
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@@ -81,9 +81,9 @@ object M68kIsa {
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IsaData("nop", "No Operation"),
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IsaData("not", "Logical Complement"),
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IsaData("or", "Logical Inclusive-OR"),
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IsaData("ori", "Logical Inclusive-OR Immediate"),
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IsaData("ori", "to CCR Inclusive-OR Immediate to Condition Code Register"),
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IsaData("ori", "to SR Inclusive-OR Immediate to Status Register"),
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IsaData("ori", "Logical Inclusive-OR Immediate", altMnemonics = listOf("or")),
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IsaData("ori", "to CCR Inclusive-OR Immediate to Condition Code Register", altMnemonics = listOf("or")),
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IsaData("ori", "to SR Inclusive-OR Immediate to Status Register", altMnemonics = listOf("or")),
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IsaData("pea", "Push Effective Address"),
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IsaData("reset", "Reset External Devices"),
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IsaData("rol", "Rotate Left"),
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@@ -97,8 +97,8 @@ object M68kIsa {
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IsaData("sCC", "Set Conditionally", conditionCodes = conditionCodes),
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IsaData("stop", "Stop"),
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IsaData("sub", "Subtract"),
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IsaData("suba", "Subtract Address"),
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IsaData("subi", "Subtract Immediate"),
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IsaData("suba", "Subtract Address", altMnemonics = listOf("sub")),
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IsaData("subi", "Subtract Immediate", altMnemonics = listOf("sub")),
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IsaData("subq", "Subtract Quick"),
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IsaData("subx", "Subtract with Extend"),
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IsaData("swap", "Swap Register Words"),
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@@ -106,7 +106,7 @@ object M68kIsa {
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IsaData("trap", "Trap"),
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IsaData("trapv", "Trap on Overflow"),
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IsaData("tst", "Test Operand"),
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IsaData("unlk", "Unlink "),
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IsaData("unlk", "Unlink"),
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)
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val mnemonics =
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@@ -206,15 +206,15 @@ AddressRegisterIndirectPostIncAddressingMode ::= ROUND_L AddressRegister ROUND_R
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AddressRegisterIndirectPreDecAddressingMode ::= OP_MINUS ROUND_L AddressRegister ROUND_R
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AddressRegisterIndirectWithDisplacementOldAddressingMode ::= expr ROUND_L AddressRegister ROUND_R
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AddressRegisterIndirectWithDisplacementNewAddressingMode ::= ROUND_L expr SEPARATOR AddressRegister ROUND_R
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AddressRegisterIndirectWithIndexOldAddressingMode ::= expr ROUND_L AddressRegister SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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AddressRegisterIndirectWithIndexNewAddressingMode ::= ROUND_L expr SEPARATOR AddressRegister SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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ProgramCounterIndirectWithDisplacementOldAddressingMode ::= expr ROUND_L PC ROUND_R
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AddressRegisterIndirectWithIndexOldAddressingMode ::= expr? ROUND_L AddressRegister SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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AddressRegisterIndirectWithIndexNewAddressingMode ::= ROUND_L (expr SEPARATOR)? AddressRegister SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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ProgramCounterIndirectWithDisplacementOldAddressingMode ::= (ROUND_L PC ROUND_R) | (expr ROUND_L PC ROUND_R)
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ProgramCounterIndirectWithDisplacementNewAddressingMode ::= ROUND_L expr SEPARATOR PC ROUND_R
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ProgramCounterIndirectWithIndexOldAddressingMode ::= expr ROUND_L PC SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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ProgramCounterIndirectWithIndexNewAddressingMode ::= ROUND_L expr SEPARATOR PC SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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ProgramCounterIndirectWithIndexOldAddressingMode ::= expr? ROUND_L PC SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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ProgramCounterIndirectWithIndexNewAddressingMode ::= ROUND_L (expr SEPARATOR)? PC SEPARATOR DataOrAddressRegister DataWidth? ROUND_R
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AbsoluteAddressAddressingMode ::= expr AddressSize? !ROUND_L
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private RegisterRange ::= (DataOrAddressRegister OP_MINUS DataOrAddressRegister)
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RegisterListAddressingMode ::= (DataOrAddressRegister|RegisterRange) (OP_AR_DIV (DataOrAddressRegister|RegisterRange))*
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RegisterListAddressingMode ::= (DataOrAddressRegister|RegisterRange) ((OP_AR_DIV|OP_MINUS) (DataOrAddressRegister|RegisterRange))*
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ImmediateData ::= HASH expr {extends=AddressingMode}
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expr ::= binary_logical_or_expr
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