From 6233cefd206aefcc08b6c38ce27aa520b38d98c6 Mon Sep 17 00:00:00 2001 From: chrisly42 Date: Thu, 25 Sep 2025 22:20:28 +0200 Subject: [PATCH] Fixed wrong carry condition code info, how could that go unnoticed so long. --- .../plugins/m68k/asm/ConditionCode.kt | 12 ++++---- .../intellij/plugins/m68k/asm/M68kIsa.kt | 30 +++++++------------ 2 files changed, 17 insertions(+), 25 deletions(-) diff --git a/src/main/java/de/platon42/intellij/plugins/m68k/asm/ConditionCode.kt b/src/main/java/de/platon42/intellij/plugins/m68k/asm/ConditionCode.kt index 7fde8f0..dccc48c 100644 --- a/src/main/java/de/platon42/intellij/plugins/m68k/asm/ConditionCode.kt +++ b/src/main/java/de/platon42/intellij/plugins/m68k/asm/ConditionCode.kt @@ -88,13 +88,13 @@ fun getCcInfo(cc: Int): Map> { CC_V_OR -> "*" to CC_OR_STR else -> "*" to "$CC_RES_STR (usually for overflows)" } - xnzvcMap["C"] = when (cc and CC_V_TST) { + xnzvcMap["C"] = when (cc and CC_C_TST) { 0 -> "-" to CC_NOT_AFFECTED_STR - CC_V_SET -> "1" to CC_ALWAYS_SET_STR - CC_V_CLEAR -> "0" to CC_ALWAYS_CLEAR_STR - CC_V_UNDEF -> "U" to CC_UNDEFINED_STR - CC_V_AND -> "*" to CC_AND_STR - CC_V_OR -> "*" to CC_OR_STR + CC_C_SET -> "1" to CC_ALWAYS_SET_STR + CC_C_CLEAR -> "0" to CC_ALWAYS_CLEAR_STR + CC_C_UNDEF -> "U" to CC_UNDEFINED_STR + CC_C_AND -> "*" to CC_AND_STR + CC_C_OR -> "*" to CC_OR_STR else -> "*" to "$CC_RES_STR (usually carry/borrow)" } diff --git a/src/main/java/de/platon42/intellij/plugins/m68k/asm/M68kIsa.kt b/src/main/java/de/platon42/intellij/plugins/m68k/asm/M68kIsa.kt index d2eb8e8..2176528 100644 --- a/src/main/java/de/platon42/intellij/plugins/m68k/asm/M68kIsa.kt +++ b/src/main/java/de/platon42/intellij/plugins/m68k/asm/M68kIsa.kt @@ -1085,7 +1085,7 @@ object M68kIsa { IsaData( "stop", "Stop", machine = ALL_MACHINES, isPrivileged = true, - modes = listOf(AllowedAdrMode(setOf(AddressMode.IMMEDIATE_DATA), null, OP_UNSIZED)) + modes = listOf(AllowedAdrMode(setOf(AddressMode.IMMEDIATE_DATA), null, OP_UNSIZED, affectedCc = cc("*****"))) ), *autoExpandForOtherCpus( @@ -1208,10 +1208,10 @@ object M68kIsa { private val mnemonicLookupMap = isaData.asSequence() .flatMap { - (if (it.conditionCodes.isEmpty()) it.altMnemonics.plus(it.mnemonic) else it.altMnemonics.plus(it.conditionCodes - .map { cc -> - it.mnemonic.replace("CC", cc) - })).map { mnemonic -> mnemonic to it } + (if (it.conditionCodes.isEmpty()) it.altMnemonics.plus(it.mnemonic) else it.altMnemonics.plus( + it.conditionCodes + .map { cc -> it.mnemonic.replace("CC", cc) })) + .map { mnemonic -> mnemonic to it } } .groupBy({ it.first }) { it.second } @@ -1223,24 +1223,16 @@ object M68kIsa { fun findMatchingOpMode(candidates: List, op1: AddressMode?, op2: AddressMode?, opSize: Int?, specialReg: String?): List { return candidates.filter { - it.modes.any { am -> - isAddressModeMatching(am, op1, op2, specialReg) - && ((opSize == null) || ((opSize and am.size) == opSize)) - } + it.modes.any { am -> isAddressModeMatching(am, op1, op2, specialReg) && ((opSize == null) || ((opSize and am.size) == opSize)) } } } fun findMatchingAddressMode(modes: List, op1: AddressMode?, op2: AddressMode?, opSize: Int?, specialReg: String?): List { - return modes.filter { am -> - isAddressModeMatching(am, op1, op2, specialReg) - && ((opSize == null) || ((opSize and am.size) == opSize)) - } + return modes.filter { am -> isAddressModeMatching(am, op1, op2, specialReg) && ((opSize == null) || ((opSize and am.size) == opSize)) } } fun findMatchingOpModeIgnoringSize(candidates: List, op1: AddressMode?, op2: AddressMode?, specialReg: String?): List { - return candidates.filter { - it.modes.any { am -> isAddressModeMatching(am, op1, op2, specialReg) } - } + return candidates.filter { it.modes.any { am -> isAddressModeMatching(am, op1, op2, specialReg) } } } fun findSupportedOpSizes(candidates: List, op1: AddressMode?, op2: AddressMode?, specialReg: String?): Int { @@ -1253,6 +1245,6 @@ object M68kIsa { private fun isAddressModeMatching(am: AllowedAdrMode, op1: AddressMode?, op2: AddressMode?, specialReg: String?) = ((((op1 == null) && (am.op1 == null)) || am.op1?.contains(op1) ?: false) - && (((op2 == null) && (am.op2 == null)) || am.op2?.contains(op2) ?: false) - && ((specialReg == null) || (am.specialReg?.split('|')?.any { it.equals(specialReg, true) } ?: false))) -} \ No newline at end of file + && (((op2 == null) && (am.op2 == null)) || am.op2?.contains(op2) ?: false) + && ((specialReg == null) || (am.specialReg?.split('|')?.any { it.equals(specialReg, true) } ?: false))) +}