Added support for movem with register list crossing from data to address (e.g. d0-a6) as found in p61a source.

This commit is contained in:
2021-08-02 09:43:42 +02:00
parent 19e3b519db
commit 7744b589d4
6 changed files with 57 additions and 4 deletions
@@ -1086,13 +1086,14 @@ public class M68kParser implements PsiParser, LightPsiParser {
}
/* ********************************************************** */
// (DataRegister OP_MINUS DataRegister) | (AddressRegister OP_MINUS AddressRegister)
// (DataRegister OP_MINUS DataRegister) | (AddressRegister OP_MINUS AddressRegister) | (DataRegister OP_MINUS AddressRegister)
public static boolean RegisterRange(PsiBuilder b, int l) {
if (!recursion_guard_(b, l, "RegisterRange")) return false;
boolean r;
Marker m = enter_section_(b, l, _NONE_, REGISTER_RANGE, "<register range>");
r = RegisterRange_0(b, l + 1);
if (!r) r = RegisterRange_1(b, l + 1);
if (!r) r = RegisterRange_2(b, l + 1);
exit_section_(b, l, m, r, false, null);
return r;
}
@@ -1121,6 +1122,18 @@ public class M68kParser implements PsiParser, LightPsiParser {
return r;
}
// DataRegister OP_MINUS AddressRegister
private static boolean RegisterRange_2(PsiBuilder b, int l) {
if (!recursion_guard_(b, l, "RegisterRange_2")) return false;
boolean r;
Marker m = enter_section_(b);
r = DataRegister(b, l + 1);
r = r && consumeToken(b, OP_MINUS);
r = r && AddressRegister(b, l + 1);
exit_section_(b, m, null, r);
return r;
}
/* ********************************************************** */
// REG_CCR | REG_SR | REG_USP | REG_VBR
public static boolean SpecialRegister(PsiBuilder b, int l) {
@@ -42,4 +42,5 @@ public class M68kProgramCounterIndirectWithIndexOldAddressingModeImpl extends M6
public M68kDataWidth getIndexWidth() {
return PsiTreeUtil.getChildOfType(this, M68kDataWidth.class);
}
}
@@ -351,7 +351,7 @@ ProgramCounterIndirectWithIndexNewAddressingMode ::= ROUND_L (expr SEPARATOR)? P
AbsoluteAddressAddressingMode ::= expr AddressSize? !ROUND_L
RegisterRange ::= (DataRegister OP_MINUS DataRegister) | (AddressRegister OP_MINUS AddressRegister) {
RegisterRange ::= (DataRegister OP_MINUS DataRegister) | (AddressRegister OP_MINUS AddressRegister) | (DataRegister OP_MINUS AddressRegister) {
name = "register range"
methods = [
startRegister = "Register[0]"
@@ -123,8 +123,12 @@ object M68kPsiImplUtil {
var startReg = Register.getRegFromName(it.startRegister.text)
val endReg = Register.getRegFromName(it.endRegister!!.text)
registers.add(startReg)
while (startReg.num < endReg.num) {
startReg = Register.getRegFromName(startReg.regname.dropLast(1) + (startReg.num + 1))
while ((startReg.num < endReg.num) || (startReg.regname.dropLast(1) != endReg.regname.dropLast(1))) {
startReg = if (startReg.num < 7) {
Register.getRegFromName(startReg.regname.dropLast(1) + (startReg.num + 1))
} else {
Register.A0 // handle wrap around from d7->a0
}
registers.add(startReg)
}
}