Added support for movem with register list crossing from data to address (e.g. d0-a6) as found in p61a source.

This commit is contained in:
2021-08-02 09:43:42 +02:00
parent 19e3b519db
commit 7744b589d4
6 changed files with 57 additions and 4 deletions
@@ -98,6 +98,17 @@ internal class AddressingModesTest : AbstractParsingTest() {
)
}
@Test
internal fun movem_register_list_with_data_address_wrapping(@MyTestCase testCase: ParsingTestExtension.IParsingTestCase) {
testGoodSyntax(testCase, " movem.l d0-a6,-(sp)\n")
val element = testCase.file.findElementAt(9)
val regList = PsiTreeUtil.getParentOfType(element, M68kRegisterListAddressingMode::class.java)!!
assertThat(regList.registers).containsExactlyInAnyOrder(
Register.D0, Register.D1, Register.D2, Register.D3, Register.D4, Register.D5, Register.D6, Register.D7,
Register.A0, Register.A1, Register.A2, Register.A3, Register.A4, Register.A5, Register.A6,
)
}
@Test
internal fun immediate_data(@MyTestCase testCase: ParsingTestExtension.IParsingTestCase) {
testGoodSyntax(testCase, " moveq.l #FOO_BAR,d0\n")
@@ -0,0 +1,24 @@
Assembly File: a.asm
PsiWhiteSpace(' ')
M68kStatementImpl(STATEMENT)
M68kAsmInstructionImpl(ASM_INSTRUCTION)
M68kAsmOpImpl(ASM_OP)
PsiElement(M68kTokenType.MNEMONIC)('movem')
M68kOperandSizeImpl(OPERAND_SIZE)
PsiElement(M68kTokenType.OPSIZE_L)('.l')
PsiWhiteSpace(' ')
M68kRegisterListAddressingModeImpl(REGISTER_LIST_ADDRESSING_MODE)
M68kRegisterRangeImpl(REGISTER_RANGE)
M68kDataRegisterImpl(DATA_REGISTER)
PsiElement(M68kTokenType.DREG)('d0')
PsiElement(M68kTokenType.OP_MINUS)('-')
M68kAddressRegisterImpl(ADDRESS_REGISTER)
PsiElement(M68kTokenType.AREG)('a6')
PsiElement(M68kTokenType.SEPARATOR)(',')
M68kAddressRegisterIndirectPreDecAddressingModeImpl(ADDRESS_REGISTER_INDIRECT_PRE_DEC_ADDRESSING_MODE)
PsiElement(M68kTokenType.OP_MINUS)('-')
PsiElement(M68kTokenType.ROUND_L)('(')
M68kAddressRegisterImpl(ADDRESS_REGISTER)
PsiElement(M68kTokenType.REG_SP)('sp')
PsiElement(M68kTokenType.ROUND_R)(')')
PsiElement(M68kTokenType.EOL)('\n')