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Full support for MC68010 ISA ('movec', 'moves' and new special registers 'SFC' and 'DFC').

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This commit is contained in:
chrisly42
2021-10-11 11:32:13 +02:00
parent 0ae17046d6
commit e0bd6981e3
10 changed files with 292 additions and 215 deletions
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src/main/java/de/platon42/intellij/plugins/m68k/asm/M68kIsa.kt
+50 -5
View File
@@ -266,6 +266,7 @@ object M68kIsa {
private val AREG_ONLY = setOf(AddressMode.ADDRESS_REGISTER_DIRECT)
private val DREG_ONLY = setOf(AddressMode.DATA_REGISTER_DIRECT)
private val DREG_AREG = setOf(AddressMode.ADDRESS_REGISTER_DIRECT, AddressMode.DATA_REGISTER_DIRECT)
private val ADD_SUB_MODES = listOf(
AllowedAdrMode(
@@ -994,6 +995,21 @@ object M68kIsa {
)
),
IsaData(
"move", "Move from Status Register", id = "move from SR", isPrivileged = true,
machine = EnumSet.range(Machine.MC68010, Machine.MC68060),
modes = listOf(
AllowedAdrMode(
setOf(AddressMode.SPECIAL_REGISTER_DIRECT),
ALL_EXCEPT_AREG_IMMEDIATE_AND_PC_REL,
OP_SIZE_W,
"sr",
modInfo = RWM_SET_OP2_W,
testedCc = cc("?????")
)
)
),
*autoExpandForOtherCpus(
MC68020_PLUS,
@@ -1017,6 +1033,38 @@ object M68kIsa {
)
),
IsaData(
"movec", "Move Control Register", isPrivileged = true,
machine = EnumSet.range(Machine.MC68010, Machine.MC68060),
modes = listOf(
AllowedAdrMode(setOf(AddressMode.SPECIAL_REGISTER_DIRECT), DREG_AREG, OP_SIZE_L, "sfc|dfc|usp|vbr", modInfo = RWM_SET_OP2_L),
AllowedAdrMode(DREG_AREG, setOf(AddressMode.SPECIAL_REGISTER_DIRECT), OP_SIZE_L, "sfc|dfc|usp|vbr", modInfo = RWM_READ_OP1_L),
)
),
IsaData(
"moves", "Move Address Space", isPrivileged = true,
machine = EnumSet.range(Machine.MC68010, Machine.MC68060),
modes = listOf(
AllowedAdrMode(
ALL_68020_MODES_EXCEPT_IMMEDIATE_AND_PC_REL.minus(
listOf(
AddressMode.DATA_REGISTER_DIRECT,
AddressMode.ADDRESS_REGISTER_DIRECT
)
), DREG_AREG, modInfo = RWM_SET_OP2_OPSIZE
),
AllowedAdrMode(
DREG_AREG, ALL_68020_MODES_EXCEPT_IMMEDIATE_AND_PC_REL.minus(
listOf(
AddressMode.DATA_REGISTER_DIRECT,
AddressMode.ADDRESS_REGISTER_DIRECT
)
), modInfo = RWM_READ_OP1_OPSIZE
)
)
),
IsaData("reset", "Reset External Devices", machine = ALL_MACHINES, isPrivileged = true, hasOps = false, modes = NO_OPS_UNSIZED),
IsaData(
"rte", "Return from Exception",
@@ -1120,10 +1168,7 @@ object M68kIsa {
private fun autoExpandForOtherCpus(machines: Set<Machine>, vararg isaDatas: IsaData): Array<out IsaData> {
val allIsaData = ArrayList<IsaData>()
for (isaData in isaDatas) {
val newModes = ArrayList<AllowedAdrMode>()
for (mode in isaData.modes) {
newModes.add(mode.copy(op1 = add68020Modes(mode.op1), op2 = add68020Modes(mode.op2)))
}
val newModes = isaData.modes.map { it.copy(op1 = add68020Modes(it.op1), op2 = add68020Modes(it.op2)) }
allIsaData.add(isaData.copy(machine = machines, modes = newModes))
}
return allIsaData.toTypedArray()
@@ -1199,5 +1244,5 @@ object M68kIsa {
private fun isAddressModeMatching(am: AllowedAdrMode, op1: AddressMode?, op2: AddressMode?, specialReg: String?) =
((((op1 == null) && (am.op1 == null)) || am.op1?.contains(op1) ?: false)
&& (((op2 == null) && (am.op2 == null)) || am.op2?.contains(op2) ?: false)
&& ((specialReg == null) || (specialReg.equals(am.specialReg, true))))
&& ((specialReg == null) || (am.specialReg?.split('|')?.any { it.equals(specialReg, true) } ?: false)))
}
src/main/java/de/platon42/intellij/plugins/m68k/lexer/_M68kLexer.flex
+2
View File
@@ -215,6 +215,8 @@ PLAIN_MACRO_LINE=[^;\r\n]+
"sr" { yybegin(exprOpState); return REG_SR; }
"usp" { yybegin(exprOpState); return REG_USP; }
"vbr" { yybegin(exprOpState); return REG_VBR; }
"dfc" { yybegin(exprOpState); return REG_DFC; }
"sfc" { yybegin(exprOpState); return REG_SFC; }
"#" { return HASH; }
"\[" { return SQUARE_L; }
src/main/java/de/platon42/intellij/plugins/m68k/m68k.bnf
+1 -1
View File
@@ -228,7 +228,7 @@ AddressRegister ::= AREG | REG_SP {
extends = Register
}
SpecialRegister ::= REG_CCR | REG_SR | REG_USP | REG_VBR {
SpecialRegister ::= REG_CCR | REG_SR | REG_USP | REG_VBR | REG_SFC | REG_DFC {
name = "special register"
extends = Register
}
src/main/java/de/platon42/intellij/plugins/m68k/syntax/M68kSyntaxHighlighter.kt
+1 -1
View File
@@ -42,7 +42,7 @@ class M68kSyntaxHighlighter(val project: Project?) : SyntaxHighlighterBase() {
M68kTypes.AREG -> arrayOf(AREG)
M68kTypes.REG_SP -> arrayOf(STACK_POINTER)
M68kTypes.DREG -> arrayOf(DREG)
M68kTypes.REG_USP, M68kTypes.REG_SR, M68kTypes.REG_CCR, M68kTypes.REG_VBR -> arrayOf(SPECIAL_REG)
M68kTypes.REG_USP, M68kTypes.REG_SR, M68kTypes.REG_CCR, M68kTypes.REG_VBR, M68kTypes.REG_SFC, M68kTypes.REG_DFC -> arrayOf(SPECIAL_REG)
M68kTypes.COMMENT -> arrayOf(COMMENT)
M68kTypes.DECIMAL, M68kTypes.HEXADECIMAL, M68kTypes.OCTAL -> arrayOf(NUMBER)
M68kTypes.STRINGLIT -> arrayOf(STRING)