chrisly42/mc68000-asm-plugin
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Enhanced ISA description (no functional changes).

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Chris Hodges 2021-07-26 15:44:13 +02:00
parent ad3b207362
commit fc5e1f6bf7
1 changed files with 148 additions and 105 deletions
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src/main/java/de/platon42/intellij/plugins/m68k/asm/M68kIsa.kt
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@ -1,121 +1,164 @@
package de.platon42.intellij.plugins.m68k.asm package de.platon42.intellij.plugins.m68k.asm
enum class Machine { enum class Machine {
MC68000 MC68000,
MC68010,
MC68020,
MC68030,
MC68040,
MC68060
} }
data class IsaData( data class IsaData(
val mnemonic: String, val mnemonic: String,
val description: String, val description: String,
val machine: Machine = Machine.MC68000, val machine: Set<Machine> = setOf(Machine.MC68000),
val altMnemonics: List<String> = emptyList(), val altMnemonics: List<String> = emptyList(),
val conditionCodes: List<String> = emptyList() val conditionCodes: List<String> = emptyList(),
val id: String = mnemonic,
val opSize: String = "bWl",
val isPrivileged: Boolean = false,
val hasOps: Boolean = true
) )
object M68kIsa { object M68kIsa {
val conditionCodes = val conditionCodes =
listOf("cc", "ls", "cs", "lt", "eq", "mi", "f", "ne", "ge", "pl", "gt", "t", "hi", "vc", "le", "vs") listOf("cc", "ls", "cs", "lt", "eq", "mi", "f", "ne", "ge", "pl", "gt", "t", "hi", "vc", "le", "vs")
val conditionCodesBcc = conditionCodes.filterNot { it == "f" || it == "t" } val conditionCodesBcc = conditionCodes.filterNot { it == "f" || it == "t" }
val isaData = listOf( val isaData = listOf(
IsaData("abcd", "Add Decimal with Extend"),
IsaData("add", "Add"), // Data Movement Instructions
IsaData("adda", "Add Address", altMnemonics = listOf("add")), IsaData("move", "Move"),
IsaData("addi", "Add Immediate", altMnemonics = listOf("add")), IsaData("movea", "Move Address", altMnemonics = listOf("move"), opSize = "L"),
IsaData("addq", "Add Quick"), IsaData("movem", "Move Multiple Registers", opSize = "Wl"),
IsaData("addx", "Add with Extend"), IsaData("movep", "Move Peripheral", opSize = ""),
IsaData("and", "Logical AND"), IsaData("moveq", "Move Quick", opSize = "L"),
IsaData("andi", "Logical AND Immediate", altMnemonics = listOf("and")),
IsaData("andi", "to CCR AND Immediate to Condition Code Register", altMnemonics = listOf("and")), IsaData("exg", "Exchange Registers", opSize = "L"),
IsaData("andi", "to SR AND Immediate to Status Register", altMnemonics = listOf("and")), IsaData("lea", "Load Effective Address", opSize = ""),
IsaData("asl", "Arithmetic Shift Left"), IsaData("pea", "Push Effective Address", opSize = ""),
IsaData("asr", "Arithmetic Shift Right"), IsaData("link", "Link and Allocate", opSize = ""),
IsaData("bCC", "Branch Conditionally", conditionCodes = conditionCodesBcc), IsaData("unlk", "Unlink", opSize = ""),
IsaData("bchg", "Test Bit and Change"),
IsaData("bclr", "Test Bit and Clear"), // Integer Arithmetic Instructions
IsaData("bra", "Branch"), IsaData("add", "Add"),
IsaData("bset", "Test Bit and Set"), IsaData("adda", "Add Address", altMnemonics = listOf("add"), opSize = "Wl"),
IsaData("bsr", "Branch to Subroutine"), IsaData("addi", "Add Immediate", altMnemonics = listOf("add")),
IsaData("btst", "Test Bit"), IsaData("addq", "Add Quick"),
IsaData("chk", "Check Register Against Bound"), IsaData("addx", "Add with Extend"),
IsaData("clr", "Clear"),
IsaData("cmp", "Compare"), IsaData("sub", "Subtract"),
IsaData("cmpa", "Compare Address", altMnemonics = listOf("cmp")), IsaData("suba", "Subtract Address", altMnemonics = listOf("sub")),
IsaData("cmpi", "Compare Immediate", altMnemonics = listOf("cmp")), IsaData("subi", "Subtract Immediate", altMnemonics = listOf("sub")),
IsaData("cmpm", "Compare Memory to Memory", altMnemonics = listOf("cmp")), IsaData("subq", "Subtract Quick"),
IsaData( IsaData("subx", "Subtract with Extend"),
"dbCC",
"Test Condition, Decrement, and Branch", IsaData("neg", "Negate"),
altMnemonics = listOf("dbra"), IsaData("negx", "Negate with Extend"),
conditionCodes = conditionCodes
), IsaData("clr", "Clear"),
IsaData("divs", "Signed Divide"),
IsaData("divu", "Unsigned Divide"), IsaData("cmp", "Compare"),
IsaData("eor", "Logical Exclusive-OR"), IsaData("cmpa", "Compare Address", altMnemonics = listOf("cmp"), opSize = "Wl"),
IsaData("eori", "Logical Exclusive-OR Immediate", altMnemonics = listOf("eor")), IsaData("cmpi", "Compare Immediate", altMnemonics = listOf("cmp")),
IsaData("eori", "to CCR Exclusive-OR Immediate to Condition Code Register", altMnemonics = listOf("eor")), IsaData("cmpm", "Compare Memory to Memory", altMnemonics = listOf("cmp")),
IsaData("eori", "to SR Exclusive-OR Immediate to Status Register", altMnemonics = listOf("eor")),
IsaData("exg", "Exchange Registers"), IsaData("muls", "Signed Multiply", opSize = "W"),
IsaData("ext", "Sign Extend"), IsaData("mulu", "Unsigned Multiply", opSize = "W"),
IsaData("illegal", "Take Illegal Instruction Trap"), IsaData("divs", "Signed Divide", opSize = "W"),
IsaData("jmp", "Jump"), IsaData("divu", "Unsigned Divide", opSize = "W"),
IsaData("jsr", "Jump to Subroutine"),
IsaData("lea", "Load Effective Address"), IsaData("ext", "Sign Extend", opSize = "Wl"),
IsaData("link", "Link and Allocate"),
IsaData("lsl", "Logical Shift Left"), // Logical Instructions
IsaData("lsr", "Logical Shift Right"), IsaData("and", "Logical AND"),
IsaData("move", "Move"), IsaData("andi", "Logical AND Immediate", altMnemonics = listOf("and")),
IsaData("movea", "Move Address", altMnemonics = listOf("move")), IsaData("eor", "Logical Exclusive-OR"),
IsaData("move", "to CCR Move to Condition Code Register"), IsaData("eori", "Logical Exclusive-OR Immediate", altMnemonics = listOf("eor")),
IsaData("move", "from SR Move from Status Register"), IsaData("not", "Logical Complement"),
IsaData("move", "to SR Move to Status Register"), IsaData("or", "Logical Inclusive-OR"),
IsaData("move", "USP Move User Stack Pointer"), IsaData("ori", "Logical Inclusive-OR Immediate", altMnemonics = listOf("or")),
IsaData("movem", "Move Multiple Registers"),
IsaData("movep", "Move Peripheral"), // Shift and Rotate Instructions
IsaData("moveq", "Move Quick"), IsaData("asl", "Arithmetic Shift Left"),
IsaData("muls", "Signed Multiply"), IsaData("asr", "Arithmetic Shift Right"),
IsaData("mulu", "Unsigned Multiply"), IsaData("lsl", "Logical Shift Left"),
IsaData("nbcd", "Negate Decimal with Extend"), IsaData("lsr", "Logical Shift Right"),
IsaData("neg", "Negate"), IsaData("rol", "Rotate Left"),
IsaData("negx", "Negate with Extend"), IsaData("ror", "Rotate Right"),
IsaData("nop", "No Operation"), IsaData("roxl", "Rotate with Extend Left"),
IsaData("not", "Logical Complement"), IsaData("roxr", "Rotate with Extend Right"),
IsaData("or", "Logical Inclusive-OR"), IsaData("swap", "Swap Register Words", opSize = ""),
IsaData("ori", "Logical Inclusive-OR Immediate", altMnemonics = listOf("or")),
IsaData("ori", "to CCR Inclusive-OR Immediate to Condition Code Register", altMnemonics = listOf("or")), // Bit Manipulation Instructions
IsaData("ori", "to SR Inclusive-OR Immediate to Status Register", altMnemonics = listOf("or")), IsaData("bchg", "Test Bit and Change", opSize = "Bl"),
IsaData("pea", "Push Effective Address"), IsaData("bclr", "Test Bit and Clear", opSize = "Bl"),
IsaData("reset", "Reset External Devices"), IsaData("bset", "Test Bit and Set", opSize = "Bl"),
IsaData("rol", "Rotate Left"), IsaData("btst", "Test Bit", opSize = "Bl"),
IsaData("ror", "Rotate Right"),
IsaData("roxl", "Rotate with Extend Left"), // Binary-Coded Decimal Instructions
IsaData("roxr", "Rotate with Extend Right"), IsaData("abcd", "Add Decimal with Extend", opSize = ""),
IsaData("rte", "Return from Exception"), IsaData("sbcd", "Subtract Decimal with Extend", opSize = ""),
IsaData("rtr", "Return and Restore"), IsaData("nbcd", "Negate Decimal with Extend", opSize = ""),
IsaData("rts", "Return from Subroutine"),
IsaData("sbcd", "Subtract Decimal with Extend"), // Program Control Instructions
IsaData("sCC", "Set Conditionally", conditionCodes = conditionCodes), IsaData("bCC", "Branch Conditionally", conditionCodes = conditionCodesBcc, opSize = "bsW"),
IsaData("stop", "Stop"), IsaData("bra", "Branch", opSize = "bsW"),
IsaData("sub", "Subtract"), IsaData("bsr", "Branch to Subroutine", opSize = "bsW"),
IsaData("suba", "Subtract Address", altMnemonics = listOf("sub")),
IsaData("subi", "Subtract Immediate", altMnemonics = listOf("sub")), IsaData(
IsaData("subq", "Subtract Quick"), "dbCC",
IsaData("subx", "Subtract with Extend"), "Test Condition, Decrement, and Branch",
IsaData("swap", "Swap Register Words"), altMnemonics = listOf("dbra"),
IsaData("tas", "Test Operand and Set"), conditionCodes = conditionCodes, opSize = "W"
IsaData("trap", "Trap"), ),
IsaData("trapv", "Trap on Overflow"), IsaData("sCC", "Set Conditionally", conditionCodes = conditionCodes, opSize = ""),
IsaData("tst", "Test Operand"),
IsaData("unlk", "Unlink"), IsaData("jmp", "Jump", opSize = ""),
) IsaData("jsr", "Jump to Subroutine", opSize = ""),
IsaData("nop", "No Operation", opSize = "", hasOps = false),
IsaData("rtr", "Return and Restore", hasOps = false),
IsaData("rts", "Return from Subroutine", hasOps = false),
IsaData("tst", "Test Operand"),
// System Control Instructions
IsaData("andi", "AND Immediate to Status Register", id = "andi to SR", altMnemonics = listOf("and"), isPrivileged = true),
IsaData("eori", "Exclusive-OR Immediate to Status Register", id = "eori to SR", altMnemonics = listOf("eor"), isPrivileged = true),
IsaData("ori", "Inclusive-OR Immediate to Status Register", id = "ori to SR", altMnemonics = listOf("or"), isPrivileged = true),
IsaData("move", "Move from Status Register", id = "move from SR"),
IsaData("move", "Move to Status Register", id = "move to SR", isPrivileged = true),
IsaData("move", "Move User Stack Pointer", id = "move USP", isPrivileged = true),
IsaData("reset", "Reset External Devices", opSize = "", isPrivileged = true, hasOps = false),
IsaData("rte", "Return from Exception", isPrivileged = true, hasOps = false),
IsaData("stop", "Stop", opSize = "", isPrivileged = true),
IsaData("chk", "Check Register Against Bound"),
IsaData("illegal", "Take Illegal Instruction Trap", opSize = "", hasOps = false),
IsaData("trap", "Trap", opSize = ""),
IsaData("trapv", "Trap on Overflow", opSize = ""),
IsaData("andi", "AND Immediate to Condition Code Register", id = "andi to CCR", altMnemonics = listOf("and")),
IsaData("eori", "Exclusive-OR Immediate to Condition Code Register", id = "eori to CCR", altMnemonics = listOf("eor")),
IsaData("ori", "Inclusive-OR Immediate to Condition Code Register", id = "ori to CCR", altMnemonics = listOf("or")),
IsaData("move", "Move to Condition Code Register", id = "move to CCR"),
// Multiprocessor Instructions
IsaData("tas", "Test Operand and Set", opSize = "B"),
)
val mnemonics = val mnemonics =
isaData.asSequence() isaData.asSequence()
.flatMap { .flatMap {
if (it.conditionCodes.isEmpty()) it.altMnemonics.plus(it.mnemonic) else it.altMnemonics.plus(it.conditionCodes if (it.conditionCodes.isEmpty()) it.altMnemonics.plus(it.mnemonic) else it.altMnemonics.plus(it.conditionCodes
.map { cc -> .map { cc ->
it.mnemonic.replace("CC", cc) it.mnemonic.replace("CC", cc)
}) })
} }
.toSet() .toSet()
} }